ATLAS ELEKTRONIK UK develop, supply and support cutting-edge maritime technology for customers worldwide. Based in Winfrith, Dorset, they work closely with the UK Royal Navy and global customers to create products which protect lives at sea.
Due to the growth of their business they are seeking an FPGA Design Engineer to join their Sonar Electronics team. The successful candidate will be supporting the delivery of bespoke electronics for integration into complex Sonar Systems, with a significant focus on high bandwidth telemetry systems. This includes the implementation of various high speed serial communication protocols, such as Gigabit Ethernet as well as data conversion and digital signal processing techniques.
The successful candidate will be enthusiastic, innovative and versatile and be able to work collaboratively as a Sonar Electronics team member and also alongside engineers in other disciplines and departments across AEUK. Additionally the successful candidate will:
- Translate customer requirements into a firmware specification.
- Create feasible preliminary architectures from the firmware specifications.
- Carry out detailed implementation of RTL, constrained Place and Route and timing closure.
- Derive verification plans to address design requirements.
- Prepare related test cases to verify that the implemented design meets the requirements.
- Design and utilise both unit level and BFM style verification test benches to exercise RTL.
- Produce accurate written documentation to fully support the design for both internal and external customers.
This is an excellent opportunity for an experienced FPGA Design Engineer who wants to challenge their technical capabilities and to develop cutting edge technologies for a world-leading organisation.
The role is based at the AEUK offices in Winfrith, Dorset, offers a significant benefit package and will require SC Clearance.
What we are looking for in you:
B.Sc. (Hons) in Electrical/Electronic Engineering (or equivalent)
Experience of a Hardware Description Language (preferably VHDL)
Proficiency in the use of a simulation tool e.g. ModelSim, Active-HDL,
Proficient in the use of Vendor design tools such as Xilinx Vivado or Altera Quartus Prime
Design and delivery of digital systems targeted at Programmable Logic Devices
IP Block design and Delivery
FPGA Verification using Self-Checking Testbenches
Producing high quality behavioural models
Use of a synthesis tool preferably (preferably Vivado)
Developing robust timing constraints and timing analysis (preferably SDC/XDC)
Scripting FPGA design, synthesis, simulation & test tools using TCL, PERL, PYTHON
Multiple clock domain designs and domain crossing techniques
Software programming language
Implementing DSP within an FPGA
Programmable SoC families such as Xilinx's Zynq